The evolution of integrated circuit (IC) fabrication technology has made possible the fabrication of microelectronic complexes, which perform a wide variety of functions and are characterized by varying degrees of complexity. Microelectronic complexes, that is systems and groups of discrete microelectronic functional modules, implement an important range of electronic devices, including microcomputers and microprocessors, and have important application in the design of electronic systems. Examples of such microelectronic complexes include Large Area Integrated Circuits (LAICs), such as semi-conductor wafers, containing a plurality of integrated circuits, as well as integrated circuits containing a plurality of microelectronic components.
The starting material for modern integrated circuits is very-high-purity silicon. The material is grown as a single crystal, which takes the shape of a solid cylinder. This cylindrical crystal is sawed to produce wafers, which are 10 to 30 cm in diameter and 200 μm thick. Certain variable properties of the crystal, notably the direction in which the crystal was crown and the number and type of impurities present, determine the basic electrical and mechanical properties of the wafer. In order to form integrated circuits on a wafer, the electrical properties of the silicon, in particular its resistivity, can be controllably altered through doping, a process by which impurities are purposely added to the pure silicon. The ability to control the doping of silicon permits the formation of diodes, transistors, and resistors in integrated circuits on the wafer.
A finished silicon wafer may contain from 100 to 1000 finished circuits. Normally, a wafer is then diced into chips, where this dicing permits the removal of defective regions. The chips are then packaged using known techniques. The resulting chip normally includes hundreds, if not thousands, of connectors, pins and wires, among other possibilities, for external connection to a circuit board, permitting signals to be exchanged between the circuits/chips and the circuit board.
A well-known problem in the field of Wafer-Scale Integration (WSI) technology is the impact of thermal expansion on external connectivity. More specifically, when a WSI microelectronic complex is connected to a circuit board by thousands of, for example, connectors positioned between the microelectronic complex and the circuit board, these connectors can be damaged due to the different rates of thermal expansion experienced by the surfaces of the microelectronic complex and the circuit board.
Taking for example a finished silicon wafer, packaged in a material such as ceramic, the wafer typically expands at a rate of 3 ppm/C. In contrast, the material of the circuit board typically expands at a rate of 20-40 ppm/C. Thus, as the two materials heat up, the two surfaces will expand at different rates, potentially damaging many of the connectors distributed between the wafer and the circuit board.
Although the impact of thermal expansion is generally known to affect the external connectivity of all different types of microelectronic complexes, it is most noticeable for LAICs characterized by dense signal interconnects requiring small and precise connections between the LAIC and the circuit board. Certain external connections between the LAIC and the circuit board, such as the power and ground wires, are larger and thus typically allow for the use of mechanical attachments, such as springs, to compensate for the difference in thermal expansion rate between materials.
Existing solutions to the problem of thermal expansion include the use of a sheet of compliant material for interfacing between the connectors of the LAIC package and the circuit board. The LAIC package has a single connection to the sheet of material, which is attached to all of the connectors of the LAIC and has the same rate of thermal expansion as the circuit board. Thus, the sheet of material “absorbs” the difference in thermal expansion between the circuit board and the LAIC package, reducing damage to the connectors caused by thermal expansion. Unfortunately, the use of additional material for interfacing between the LAIC and the circuit board is an expensive solution, which reduces the yield of the LAIC. Further, the sheet of material typically interferes with cooling of the LAIC, where such cooling is required to prevent overheating of the LAIC.
Another existing solution involves the packaging of the LAIC in a ceramic package, where the LAIC is connected on a ceramic board which itself is mounted to the circuit board. The ceramic board is characterized by a thermal expansion coefficient value that is intermediate the thermal expansion coefficient values of the LAIC and the circuit board, for reducing the effects of thermal expansion on the connectivity between the LAIC and the circuit board. Unfortunately, interfacing the LAIC and the circuit board with a material of intermediate thermal expansion does not solve the problem, but rather simply delays the impacts of thermal expansion on the connections. Although the use of a ceramic board initially renders the external connectivity of the LAIC stronger, the damage by thermal expansion will typically still occur over time.
Thus, existing solutions to reduce the damage caused by thermal expansion to the external connectivity of microelectronic complexes typically require the use of additional material for interfacing or buffering between the microelectronic complex and the circuit board. Such solutions obviously increase the cost associated with the manufacture of microelectronic complexes and/or the mounting of microelectronic complexes to circuit boards, and may also be detrimental to the quality of the external connectivity between the microelectronic complex and the circuit board.
Against this background, a need exists in the industry for an improved method and apparatus providing a reduction in thermal expansion effects on the external connectivity of a microelectronic complex.